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a functional block diagram clock generation serial interface output register charge-balancing a/d converter auto-zeroed s C d modulator digital filter ad7712 agnd dgnd mode sdata sclk a0 mclk out mclk in ain1(C) ref in (C) ref in (+) sync 4.5 m a a = 1 C 128 drdy tfs rfs ref out v bias voltage attenuation ain2 tp standby control register v ss 2.5v reference dv dd av dd av dd m u x ain1(+) pga features charge balancing adc 24 bits no missing codes 6 0.0015% nonlinearity high level and low level analog input channels programmable gain for both inputs gains from 1 to 128 differential input for low level channel low-pass filter with programmable filter cutoffs ability to read/write calibration coefficients bidirectional microcontroller serial interface internal/external reference option single or dual supply operation low power (25 mw typ) with power-down mode (100 m w typ) applications process control smart transmitters portable industrial instruments lc 2 mos signal conditioning adc rev. e information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. general description the ad7712 is a complete analog front end for low frequency measurement applications. the device has two analog input channels and accepts either low level signals directly from a transducer or high level ( 4 v ref ) signals and outputs a serial digital word. it employs a sigma-delta conversion technique to realize up to 24 bits of no missing codes performance. the low level input signal is applied to a proprietary programmable gain front end based around an analog modulator. the high level analog input is attenuated before being applied to the same modulator. the modulator output is processed by an on-chip digital filter. the first notch of this digital filter can be pro- grammed via the on-chip control register allowing adjustment of the filter cutoff and settling time. normally, one of the channels will be used as the main channel with the second channel used as an auxiliary input to periodi- cally measure a second voltage. the part can be operated from a single supply (by tying the v ss pin to agnd) provided that the input signals on the low level analog input are more positive than C30 mv. by taking the v ss pin negative, the part can con- vert signals down to Cv ref on this low level input. this low level input, as well as the reference input, features differential input capability. the ad7712 is ideal for use in smart, microcontroller-based systems. input channel selection, gain settings and signal polar- ity can be configured in software using the bidirectional serial one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: 781/326-8703 ? analog devices, inc., 1998 port. the ad7712 also contains self-calibration, system calibra- tion and background calibration options and also allows the user to read and to write the on-chip calibration registers. cmos construction ensures low power dissipation and a hard- ware programmable power-down mode reduces the standby power consumption to only 100 m w typical. the part is avail- able in a 24-lead, 0.3 inch wide, plastic and hermetic dual-in- line package (dip) as well as a 24-lead small outline (soic) package. product highlights 1. the low level analog input channel allows the ad7712 to accept input signals directly from a strain gage or transducer, removing a considerable amount of signal conditioning. to maximize the flexibility of the part, the high level analog input accepts signals of 4 v ref /gain. 2. the ad7712 is ideal for microcontroller or dsp processor applications with an on-chip control register that allows control over filter cutoff, input gain, channel selection, signal polarity and calibration modes. 3. the ad7712 allows the user to read and to write the on-chip calibration registers. this means that the microcontroller has much greater control over the calibration procedure. 4. no missing codes ensures true, usable, 23-bit dynamic range coupled with ex cellent 0.0015% accuracy. the effects of temperature drift are eliminated by on-chip self-calibration, which removes zero-scale and full-scale errors. ad7712* * protected by u.s. patent no. 5,134,401.
parameter a, s versions 1 units conditions/comments static performance no missing codes 24 bits min guaranteed by design. for filter notches 60 hz 22 bits min for filter notch = 100 hz 18 bits min for filter notch = 250 hz 15 bits min for filter notch = 500 hz 12 bits min for filter notch = 1 khz output noise see tables i & ii depends on filter cutoffs and selected gain integral nonlinearity @ +25 c 0.0015 % fsr max filter notches 60 hz t min to t max 0.003 % fsr max typically 0.0003% positive full-scale error 2, 3 see note 4 excluding reference full-scale drift 5 1 m v/ c typ excluding reference. for gains of 1, 2 0.3 m v/ c typ excluding reference. for gains of 4, 8, 16, 32, 64, 128 unipolar offset error 2 see note 4 unipolar offset drift 5 0.5 m v/ c typ for gains of 1, 2 0.25 m v/ c typ for gains of 4, 8, 16, 32, 64, 128 bipolar zero error 2 see note 4 bipolar zero drift 5 0.5 m v/ c typ for gains of 1, 2 0.25 m v/ c typ for gains of 4, 8, 16, 32, 64, 128 gain drift 2 ppm/ c typ bipolar negative full-scale error 2 @ +25 c 0.003 % fsr max excluding reference t min to t max 0.006 % fsr max typically 0.0006% bipolar negative full-scale drift 5 1 m v/ c typ excluding reference. for gains of 1, 2 0.3 m v/ c typ excluding reference. for gains of 4, 8, 16, 32, 64, 128 analog inputs/reference inputs normal-mode 50 hz rejection 6 100 db min for filter notches of 10 hz, 25 hz, 50 hz, 0.02 f notch normal-mode 60 hz rejection 6 100 db min for filter notches of 10 hz, 30 hz, 60 hz, 0.02 f notch ain1/ref in dc input leakage current @ +25 c 6 10 pa max t min to t max 1 na max sampling capacitance 6 20 pf max common-mode rejection (cmr) 100 db min at dc common-mode 50 hz rejection 6 150 db min for filter notches of 10 hz, 25 hz, 50 hz, 0.02 f notch common-mode 60 hz rejection 6 150 db min for filter notches of 10 hz, 30 hz, 60 hz, 0.02 f notch common-mode voltage range 7 v ss to av dd v min to v max analog inputs 8 input sampling rate, f s see table iii ain1 input voltage range 9 for normal operation. depends on gain selected 0 to +v ref 10 v max unipolar input range (b/u bit of control register = 1) v ref v max bipolar input range (b/u bit of control register = 0) ain2 input voltage range 9 for normal operation. depends on gain selected 0 to + 4 v ref 10 v max unipolar input range (b/u bit of control register = 1) 4 v ref v max bipolar input range (b/u bit of control register = 0) ain2 dc input impedance 30 k w ain2 gain error 11 0.05 % typ additional error contributed by resistor attenuator ain2 gain drift 1 ppm/ c typ additional drift contributed by resistor attenuator ain2 offset error 11 10 mv max additional error contributed by resistor attenuator ain2 offset drift 20 m v/ c typ reference inputs ref in(+) C ref in(C) voltage 12 +2.5 to +5 v min to v max for specified performance. part is functional with lower v ref voltages input sampling rate, f s f clk in /256 notes 1 temperature range is as follows: a version, C40 c to +85 c; s version C55 c to +125 c. see also note 18. 2 applies after calibration at the temperature of interest. 3 positive full-scale error applies to both unipolar and bipolar input ranges. 4 these errors will be of the order of the output noise of the part as shown in table i after system calibration. these errors wi ll be 20 m v typical after self-calibration or background calibration. 5 recalibration at any temperature or use of the background calibration mode will remove these drift errors. 6 these numbers are guaranteed by design and/or characterization. 7 this common-mode voltage range is allowed provided that the input voltage on ain1(+) and ain1(C) does not exceed av dd + 30 mv and v ss C 30 mv. 8 the ain1 analog input presents a very high impedance dynamic load which varies with clock frequency and input sample rate. the maximum recommended source resistance depends on the selected gain (see tables iv and v). 9 the analog input voltage range on the ain1(+) input is given here with respect to the voltage on the ain1(C) input. the input v oltage range on the ain2 input is with respect to agnd. the absolute voltage on the ain1 input should not go more positive than av dd + 30 mv or more negative than v ss C 30 mv. 10 v ref = ref in(+) C ref in(C). 11 this error can be removed using the system calibration capabilities of the ad7712. this error is not removed by the ad7712s se lf-calibration features. the offset drift on the ain2 input is 4 times the value given in the static performance section. 12 the reference input voltage range may be restricted by the input voltage range requirement on the v bias input. C2C rev. e (av dd = +5 v 6 5%; dv dd = +5 v 6 5%; v ss = 0 v or C5 v 6 5%; ref in(+) = +2.5 v; ref in(C) = agnd; mclk in = 10 mhz unless otherwise stated. all specifications t min to t max unless otherwise noted.) ad7712Cspecifications
parameter a, s versions 1 units conditions/comments reference output output voltage 2.5 v nom initial tolerance 1 % max drift 20 ppm/ c typ output noise 30 m v typ pk-pk noise; 0.1 hz to 10 hz bandwidth line regulation (av dd ) 1 mv/v max load regulation 1.5 mv/ma max maximum load current 1 ma external current 1 ma max v bias input 13 input voltage range av dd C 0.85 v ref see v bias input section or av dd C 3.5 v max whichever is smaller; +5 v/C5 v or +10 v/0 v nominal av dd /v ss or av dd C 2.1 v max whichever is smaller; +5 v/0 v nominal av dd /v ss v ss + 0.85 v ref see v bias input section or v ss + 3 v min whichever is greater; +5 v/C5 v or +10 v/0 v nominal av dd /v ss or v ss + 2.1 v min whichever is greater; +5 v/0 v nominal av dd /v ss v bias rejection 65 to 85 db typ increasing with gain logic inputs input current 10 m a max all inputs except mclk in v inl , input low voltage 0.8 v max v inh , input high voltage 2.0 v min mclk in only v inl , input low voltage 0.8 v max v inh , input high voltage 3.5 v min logic outputs v ol , output low voltage 0.4 v max i sink = 1.6 ma v oh , output high voltage 4.0 v min i source = 100 m a floating state leakage current 10 m a max floating state output capacitance 14 9 pf typ transducer burnout current 4.5 m a nom initial tolerance 10 % typ drift 0.1 %/ c typ system calibration ain1 positive full-scale calibration limit 15 (1.05 v ref )/gain v max gain is the selected pga gain (between 1 and 128) negative full-scale calibration limit 15 C(1.05 v ref )/gain v max gain is the selected pga gain (between 1 and 128) offset calibration limit 16, 17 C(1.05 v ref )/gain v max gain is the selected pga gain (between 1 and 128) input span 15 0.8 v ref /gain v min gain is the selected pga gain (between 1 and 128) (2.1 v ref )/gain v max gain is the selected pga gain (between 1 and 128) ain2 positive full-scale calibration limit 15 (4.2 v ref )/gain v max gain is the selected pga gain (between 1 and 128) negative full-scale calibration limit 15 C(4.2 v ref )/gain v max gain is the selected pga gain (between 1 and 128) offset calibration limit 17 C(4.2 v ref )/gain v max gain is the selected pga gain (between 1 and 128) input span 15 3.2 v ref /gain v min gain is the selected pga gain (between 1 and 128) (8.4 v ref )/gain v max gain is the selected pga gain (between 1 and 128) notes 13 the ad7712 is tested with the following v bias voltages. with av dd = +5 v and v ss = 0 v, v bias = +2.5 v; with av dd = +10 v and v ss = 0 v, v bias = +5 v and with av dd = +5 v and v ss = C5 v, v bias = 0 v. 14 guaranteed by design, not production tested. 15 after calibration, if the analog input exceeds positive full scale, the converter will output all 1s. if the analog input is le ss than negative full scale, then the device will output all 0s. 16 these calibration and span limits apply provided the absolute voltage on the ain1 analog inputs does not exceed av dd + 30 mv or does not go more negative than v ss C 30 mv. 17 the offset calibration limit applies to both the unipolar zero point and the bipolar zero point. ad7712 C3C rev. e
parameter a, s versions 1 units conditions/comments power requirements power supply voltages av dd voltage 18 +5 to +10 v nom 5% for specified performance dv dd voltage 19 +5 v nom 5% for specified performance av dd C v ss voltage +10.5 v max for specified performance power supply currents av dd current 4 ma max dv dd current 4.5 ma max v ss current 1.5 ma max v ss = C5 v power supply rejection 20 rejection w.r.t. agnd; assumes v bias is fixed positive supply (av dd and dv dd ) see note 21 db typ negative supply (v ss ) 90 db typ power dissipation normal mode 45 mw max av dd = dv dd = +5 v, v ss = 0 v; typically 25 mw normal mode 52.5 mw max av dd = dv dd = +5 v, v ss = C5 v; typically 30 mw standby (power-down) mode 22 200 m w max av dd = dv dd = +5 v, v ss = 0 v or C5 v; typically 100 m w notes 18 the ad7712 is specified with a 10 mhz clock for av dd voltages of +5 v 5%. it is specified with an 8 mhz clock for av dd voltages greater than 5.25 v and less than 10.5 v. 19 the 5% tolerance on the dv dd input is allowed provided that dv dd does not exceed av dd by more than 0.3 v. 20 measured at dc and applies in the selected passband. psrr at 50 hz will exceed 120 db with filter notches of 10 hz, 25 hz or 50 hz. psrr at 60 hz will exceed 120 db with filter notches of 10 hz, 30 hz or 60 hz. 21 psrr depends on gain: gain of 1 = 70 db typ; gain of 2 = 75 db typ; gain of 4 = 80 db typ; gains of 8 to 128 = 85 db typ. these numbers can be improved (to 95 db typ) by deriving the v bias voltage (via zener diode or reference) from the av dd supply. 22 using the hardware standby pin. standby power dissipation using the software standby bit (pd) of the control register is 8 mw t yp. specifications subject to change without notice. ad7712Cspecifications rev. e C4C caution esd (electrostatic discharge) sensitive device. the digital control inputs are diode protected; however, permanent damage may occur on unconnected devices subject to high energy electro- static fields. unused devices must be stored in conductive foam or shunts. the protective foam should be discharged to the destination socket before devices are inserted. ref out to agnd . . . . . . . . . . . . . . . . . . . . C0.3 v to av dd digital input voltage to dgnd . . . . . C0.3 v to av dd + 0.3 v digital output voltage to dgnd . . . C0.3 v to dv dd + 0.3 v operating temperature range commercial (a version) . . . . . . . . . . . . . . . C40 c to +85 c extended (s version) . . . . . . . . . . . . . . . . . C55 c to +125 c storage temperature range . . . . . . . . . . . . . C65 c to +150 c lead temperature (soldering, 10 secs) . . . . . . . . . . . . +300 c power dissipation (any package) to +75 c . . . . . . . . 450 mw *stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of the specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. absolute maximum ratings* (t a = +25 c, unless otherwise noted) av dd to dv dd . . . . . . . . . . . . . . . . . . . . . . . C0.3 v to +12 v av dd to v ss . . . . . . . . . . . . . . . . . . . . . . . . . . . C0.3 v to +12 v av dd to agnd . . . . . . . . . . . . . . . . . . . . . . C0.3 v to +12 v av dd to dgnd . . . . . . . . . . . . . . . . . . . . . . C0.3 v to +12 v dv dd to agnd . . . . . . . . . . . . . . . . . . . . . . . C0.3 v to +6 v dv dd to dgnd . . . . . . . . . . . . . . . . . . . . . . . C0.3 v to +6 v v ss to agnd . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 v to C6 v v ss to dgnd . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 v to C6 v ain1 input voltage to agnd . . v ss C 0.3 v to av dd + 0.3 v reference input voltage to agnd . . . . . . . . . . . . . . . . . . . . . . . . . v ss C 0.3 v to av dd + 0.3 v ordering guide model temperature range package options* ad7712an C40 c to +85 c n-24 ad7712ar C40 c to +85 c r-24 ad7712aq C40 c to +85 cq-24 ad7712sq C55 c to +125 cq-24 eval-ad7712eb evaluation board *n = plastic dip, q = cerdip; r = soic. warning! esd sensitive device
2 C5C rev. e ad7712 timing characteristics 1, 2 limit at t min , t max parameter (a, s versions) units conditions/comments f clk in 4, 5 master clock frequency: crystal oscillator or externally supplied 400 khz min av dd = +5 v 5% 10 mhz max for specified performance 8 mhz av dd = +5.25 v to +10.5 v t clk in lo 0.4 t clk in ns min master clock input low time; t clk in = 1/f clk in t clk in hi 0.4 t clk in ns min master clock input high time t r 6 50 ns max digital output rise time; typically 20 ns t f 6 50 ns max digital output fall time; typically 20 ns t 1 1000 ns min sync pulsewidth self-clocking mode t 2 0 ns min drdy to rfs setup time; t clk in = 1/f clk in t 3 0 ns min drdy to rfs hold time t 4 2 t clk in ns min a0 to rfs setup time t 5 0 ns min a0 to rfs hold time t 6 4 t clk in + 20 ns max rfs low to sclk falling edge t 7 7 4 t clk in + 20 ns max data access time ( rfs low to data valid) t 8 7 t clk in /2 ns min sclk falling edge to data valid delay t clk in /2 + 30 ns max t 9 t clk in /2 ns nom sclk high pulsewidth t 10 3 t clk in /2 ns nom sclk low pulsewidth t 14 50 ns min a0 to tfs setup time t 15 0 ns min a0 to tfs hold time t 16 4 t clk in + 20 ns max tfs to sclk falling edge delay time t 17 4 t clk in ns min tfs to sclk falling edge hold time t 18 0 ns min data valid to sclk setup time t 19 10 ns min data valid to sclk hold time (dv dd = +5 v 6 5%; av dd = +5 v or +10 v 3 6 5%; v ss = 0 v or C5 v 6 5%; agnd = dgnd = 0 v; f clkin =10 mhz; input logic 0 = 0 v, logic 1 = dv dd unless otherwise noted.)
rev. e C6C ad7712 limit at t min , t max parameter (a, s versions) units conditions/comments external clocking mode f sclk f clk in /5 mhz max serial clock input frequency t 20 0 ns min drdy to rfs setup time t 21 0 ns min drdy to rfs hold time t 22 2 t clk in ns min a0 to rfs setup time t 23 0 ns min a0 to rfs hold time t 24 7 4 t clk in ns max data access time ( rfs low to data valid) t 25 7 10 ns min sclk falling edge to data valid delay 2 t clk in + 20 ns max t 26 2 t clk in ns min sclk high pulse width t 27 2 t clk in ns min sclk low pulse width t 28 t clk in + 10 ns max sclk falling edge to drdy high t 29 8 10 ns min sclk to data valid hold time t clk in + 10 ns max t 30 10 ns min rfs / tfs to sclk falling edge hold time t 31 8 5 t clk in /2 + 50 ns max rfs to data valid hold time t 32 0 ns min a0 to tfs setup time t 33 0 ns min a0 to tfs hold time t 34 4 t clk in ns min sclk falling edge to tfs hold time t 35 2 t clk in C sclk high ns min data valid to sclk setup time t 36 30 ns min data valid to sclk hold time notes 1 guaranteed by design, not production tested. sample tested during initial release and after any redesign or process change that may affect this parameter. all input signals are specified with tr = tf = 5 ns (10% to 90% of 5 v) and timed from a voltage level of 1.6 v. 2 see figures 11 to 14. 3 the ad7712 is specified with a 10 mhz clock for av dd voltages of +5 v 5%. it is specified with an 8 mhz clock for av dd voltages greater than 5.25 v and less than 10.5 v. 4 clk in duty cycle range is 45% to 55%. clk in must be supplied whenever the ad7712 is not in standby mode. if no clock is prese nt in this case, the device can draw higher current than specified and possibly become uncalibrated. 5 the ad7712 is production tested with f clk in at 10 mhz (8 mhz for av dd < +5.25 v). it is guaranteed by characterization to operate at 400 khz. 6 specified using 10% and 90% points on waveform of interest. 7 these numbers are measured with the load circuit of figure 1 and defined as the time required for the output to cross 0.8 v or 2.4 v. 8 these numbers are derived from the measured time taken by the data output to change 0.5 v when loaded with the circuit of figur e 1. the measured number is then extrapolated back to remove effects of charging or discharging the 100 pf capacitor. this means that the times quoted i n the timing characteristics are the true bus relinquish times of the part and, as such, are independent of external bus loading capacitances. specifications subject to change without notice. to output pin +2.1v 1.6ma 200 m a 100pf figure 1. load circuit for access time and bus relinquish time pin configuration dip and soic top view (not to scale) 24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 ad7712 av dd v ss tp standby ain1(C) mclk in mclk out a0 ain1(+) mode sclk sync v bias ref in(C) ref in(+) ref out ain2 dgnd dv dd sdata drdy agnd tfs rfs
2 C7C rev. e ad7712 pin function description pin mnemonic function 1 sclk serial clock. logic input/output depending on the status of the mode pin. when mode is high, the device is in its self-clocking mode and the sclk pin provides a serial clock output. this sclk becomes active when rfs or tfs goes low and it goes high impedance when either rfs or tfs returns high or when the device has completed transmission of an output word. when mode is low, the device is in its external clocking mode and the sclk pin acts as an input. this input serial clock can be a continuous clock with all data transmitted in a continuous train of pulses. alternatively, it can be a noncontinuous clock with the information being transmitted to the ad7712 in smaller batches of data. 2 mclk in master clock signal for the de vice. t his can be provided in the form of a crystal or external clock. a crys tal can be tied across the mclk in and mclk out pins. alternatively, the mclk in pin can be driven with a cmos-compatible clock and mclk out left unconnected. the clock input frequency is nominally 10 mhz. 3 mclk out when the m aster clock for the device is a crystal, the crystal is connected between mclk in and mclk out. 4 a0 address input. with this input low, reading and writing to the device is to the control register. with this input high, access is to either the data register or the calibration registers. 5 sync logic in put which allows for synchronization of the digital filters when using a number of ad771 2s. it resets the nodes of the digital filter. 6 mode logic input. w hen this pin is high, the device is in its self-clocking mode; with this pin low, the device is in its external clocking mode. 7 ain1(+) analog input channel 1. positive input of the programmable gain differential analog input. the ain1(+) input is connected to an output current source which can be used to check that an external transducer has burned out or gone open circuit. this output current source can be turned on/off via the control register. 8 ain1(C) analog input channel 1. negative input of the programmable gain differential analog input. 9 standby logic input. taking this pin low shuts down the internal analog and digital circuitry, reducing power consumption to less than 50 m w. 10 tp test pin. used when testing the device. do not connect anything to this pin. 11 v ss analog negative supply, 0 v to C5 v. tied to agnd for single supply operation. the input voltage on ain1 should not go > 30 mv negative w.r.t. v ss for correct operation of the device. 12 av dd analog positive supply voltage, +5 v to +10 v. 13 v bias input bias voltage. this input voltage should be set such that v bias + 0.85 v ref < av dd and v bias C 0.85 v ref > v ss where v ref is ref in(+) C ref in(C). ideally, this should be tied halfway between av dd and v ss . thus, with av dd = +5 v and v ss = 0 v, it can be tied to ref out; with av dd = +5 v and v ss = C5 v, it can be tied to agnd, while with av dd = +10 v, it can be tied to +5 v. 14 ref in(C) reference input. the ref in(C) can lie anywhere between av dd and v ss provided ref in(+) is greater than ref in(C). 15 ref in(+) reference input. the reference input is differential providing that ref in(+) is greater than ref in(C). ref in(+) can lie anywhere between av dd and v ss . 16 ref out reference output. the internal +2.5 v reference is provided at this pin. this is a single-ended output which is referred to agnd. 17 ain2 analog input channel 2. high level analog input which accepts an analog input voltage range of 4 v ref /gain. at the nominal v ref of +2.5 v and a gain of 1, the ain2 input voltage range is 10 v. 18 agnd ground reference point for analog circuitry. 19 tfs transmit frame synchronization. active low logic input used to write serial data to the device with serial data expected after the falling edge of this pulse. in the self-clocking mode, the serial clock becomes active after tfs goes low. in the external clocking mode, tfs must go low before the first bit of the data word is written to the part. 20 rfs receive frame synchronization. active low logic input used to access serial data from the device. in the self-clocking mode, the sclk and sdata lines both become active after rfs goes low. in the external clocking mode, the sdata line becomes active after rfs goes low.
rev. e C8C ad7712 pin mnemonic function 21 drdy logic output. a falling edge indicates that a new output word is available for transmission. the drdy pin will return high upon completion of transmission of a full output word. drdy is also used to indicate when the ad7712 has completed its on-chip calibration sequence. 22 sdata serial data. input/output with serial data being written to either the control register or the calibration registers and serial data being accessed from the control register, calibration registers or the data register. during an output data read operation, serial data becomes active after rfs goes low (provided drdy is low). during a write operation, valid serial data is expected on the rising edges of sclk when tfs is low. the output data coding is natural binary for unipolar inputs and offset binary for bipolar inputs. 23 dv dd digital supply voltage, +5 v. dv dd should not exceed av dd by more than 0.3 v in normal operation. 24 dgnd ground reference point for digital circuitry. terminology integral nonlinearity this is the maximum deviation of any code from a straight line passing through the endpoints of the transfer function. the end- points of the transfer function are zero-scale (not to be confused with bipolar zero), a point 0.5 lsb below the first code transi- tion (000 . . . 000 to 000 . . . 001) and full scale, a point 0.5 lsb above the last code transition (111 . . . 110 to 111 . . . 111). the error is expressed as a percentage of full scale. positive full-scale error positive full-scale error is the deviation of the last code transi- tion (111 . . . 110 to 111 . . . 111) from the ideal input full-scale voltage. for ain1(+), the ideal full-scale input voltage is (ain1(C) + v ref /gain C 3/2 lsbs); for ain2, the ideal full- scale voltage is +4 v ref /gain C 3/2 lsbs. positive full-scale error applies to both unipolar and bipolar analog input ranges. unipolar offset error unipolar offset error is the deviation of the first code transition from the ideal voltage. for ain1(+), the ideal input voltage is (ain1(C) + 0.5 lsb); for ain2, the ideal input is 0.5 lsb when operating in the unipolar mode. bipolar zero error this is the deviation of the midscale transition (0111 . . . 111 to 1000 . . . 000) from the ideal input voltage. for ain1(+), the ideal input voltage is (ain1(C) C 0.5 lsb); for ain2, the ideal input is C0.5 lsb when operating in the bipolar mode. bipolar negative full-scale error this is the deviation of the first code transition from the ideal input voltage. for ain1(+), the ideal input voltage is (ain1(C) C v ref /gain + 0.5 lsb); for ain2, the ideal input voltage is (C4 v ref /gain + 0.5 lsb) when operating in the bipolar mode. positive full-scale overrange positive full-scale overrange is the amount of overhead available to handle input voltages on ain1(+) input greater than (ain1(C) + v ref /gain) or on the ain2 of greater than +4 v ref /gain (for example, noise peaks or excess voltages due to system gain errors in system calibration routines) without intro- ducing errors due to overloading the analog modulator or to overflowing the digital filter. negative full-scale overrange this is the amount of overhead available to handle voltages on ain1(+) below (ain1(C) C v ref /gain) or on ain2 below C4 v ref /gain without overloading the analog modulator or overflowing the digital filter. note that the analog input will accept negative voltage peaks on ain1(+) even in the unipolar mode provided that ain1(+) is greater than ain1(C) and greater than v ss C 30 mv. offset calibration range in the system calibration modes, the ad7712 calibrates its offset with respect to the analog input. the offset calibration range specification defines the range of voltages that the ad7712 can accept and still accurately calibrate offset. full-scale calibration range this is the range of voltages that the ad7712 can accept in the system calibration mode and still correctly calibrate full-scale. input span in system calibration schemes, two voltages applied in sequence to the ad7712s analog input define the analog input range. the input span specification defines the minimum and maxi- mum input voltages from zero to full-scale that the ad7712 can accept and still accurately calibrate gain.
2 C9C rev. e ad7712 control register (24 bits) a write to the device with the a0 input low writes data to the control register. a read to the device with the a0 input low acc esses the contents of the control register. the control register is 24-bits wide and when writing to the register 24 bits of data must be written otherwise the data will not be loaded to the control register. in other words, it is not possible to write just the first 12-bi ts of data into the control register. if more than 24 clock pulses are provided before tfs returns high, then all clock pulses after the 24th clock pulse are ignored. similarly, a read operation from the control register should access 24 bits of data. msb md2 md1 md0 g2 g1 g0 ch pd wl x bo b/u fs11 fs10 fs9 fs8 fs7 fs6 fs5 fs4 fs3 fs2 fs1 fs0 lsb x = dont care. operating mode md2 md1 md0 operating mode 0 0 0 normal mode. this is the normal mode of operation of the device whereby a read to the device accesses data from the data register. this is the default condition of these bits after the internal power on reset. 0 0 1 activate self-calibration. this activates self-calibration on the channel selected by ch. this is a one-step calibration sequence, and when complete, the part returns to normal mode (with md2, md1, md0 of the control registers returning to 0, 0, 0). the drdy output indicates when this self-calibration is complete. for this calibration type, the zero-scale calibration is done internally on shorted (zeroed) inputs and the full-scale calibration is done on v ref . 0 1 0 activate system calibration. this activates system calibration on the channel selected by ch. this is a two-step calibration sequence, with the zero-scale calibration done first on the selected input channel and drdy indicating when this zero-scale calibration is complete. the part returns to normal mode at the end of this first step in the two-step sequence. 0 1 1 activate system calibration. this is the second step of the system calibration sequence with full-scale calibration being performed on the selected input channel. once again, drdy indicates when the full- scale calibration is complete. when this calibration is complete, the part returns to normal mode. 1 0 0 activate system offset calibration. this activates system offset calibration on the channel selected by ch. this is a one-step calibration sequence and, when complete, the part returns to normal mode with drdy indicating when this system offset calibration is complete. for this calibration type, the zero-scale calibration is done on the selected input channel and the full-scale calibration is done internally on v ref . 1 0 1 activate background calibration. this activates background calibration on the channel selected by ch. if the background calibration mode is on, then the ad7712 provides continuous self-calibration of the reference and shorted (zeroed) inputs. this calibration takes place as part of the conversion sequence, extending the conversion time and reducing the word rate by a factor of six. its major advantage is that the user does not have to worry about recalibrating the device when there is a change in the ambient temperature. in this mode, the shorted (zeroed) inputs and v ref , as well as the analog input voltage, are continuously monitored and the calibration registers of the device are automatically updated. 1 1 0 read/write zero-scale calibration coefficients. a read to the device with a0 high accesses the contents of the zero-scale calibration coefficients of the channel selected by ch. a write to the device with a0 high writes data to the zero-scale calibration coefficients of the channel selected by ch. the word length for reading and writing these coefficients is 24 bits, regardless of the status of the wl bit of the control register. therefore, when writing to the calibration register, 24 bits of data must be written, otherwise the new data will not be transferred to the calibration register. 1 1 1 read/write full-scale calibration coefficients. a read to the device with a0 high accesses the contents of the full-scale calibration coefficients of the channel selected by ch. a write to the device with a0 high writes data to the full-scale calibration coefficients of the channel selected by ch. the word length for reading and writing these coefficients is 24 bits, regardless of the status of the wl bit of the control register. therefore, when writing to the calibration register, 24 bits of data must be written, otherwise the new data will not be transferred to the calibration register.
rev. e C10C ad7712 pga gain g2 gl g0 gain 0 0 0 1 (default condition after the internal power-on reset) 00 1 2 01 0 4 01 1 8 10 0 16 10 1 32 11 0 64 1 1 1 128 channel selection ch channel 0 ain1 low level input (default condition after the internal power-on reset) 1 ain2 high level input power-down pd 0 normal operation (default condition after the internal power-on reset) 1 power-down word length wl output word length 0 16-bit (default condition after internal power-on reset) 1 24-bit burnout current bo 0 off (default condition after internal power-on reset) 1on bipolar/unipolar selection (both inputs) b/u 0 bipolar (default condition after internal power-on reset) 1 unipolar filter selection (fs11Cfs0) the on-chip digital filter provides a sinc 3 (or (sinx/x) 3 ) filter response. the 12 bits of data programmed into these bits determine the filter cutoff frequency, the position of the first notch of the filter and the data rate for the part. in association with the gain selec- tion, it also determines the output noise (and hence the effective resolution) of the device. the first notch of the filter occurs at a frequency determined by the relationship: filter first notch frequency = (f clk in /512)/ code where code is the decimal equivalent of the code in bits fs0 to fs11 and is in the range 19 to 2,000. with the nominal f clk in of 10 mhz, this results in a first notch frequency range from 9.76 hz to 1.028 khz. to ensure correct operation of the ad7712, the value of the code loaded to these bits must be within this range. failure to do this will result in unspecified operation of th e device. changing the filter notch frequency, as well as the selected gain, impacts resolution. tables i and ii and figure 2 show the ef fect of the filter notch frequency and gain on the effective resolution of the ad7712. the output data rate (or effective conversion ti me) for the device is equal to the frequency selected for the first notch of the filter. for example, if the first notch of the filter is selected at 50 hz, then a new word is available at a 50 hz rate or every 20 ms. if the first notch is at 1 khz, a new word is available every 1 ms. the settling time of the filter to a full-scale step input change is worst case 4 1/(output data rate). this settling time is to 100% of the final value. for example, with the first filter notch at 50 hz, the settling time of the filter to a full-scale step input change is 80 ms max. if the first notch is at 1 khz, the settling time of the filter to a full-scale input step is 4 ms max. this settlin g time can be reduced to 3 l/(output data rate) by synchronizing the step input change to a reset of the digital filter. in other words, if the step input takes place with sync low, the settling time will be 3 l/(output data rate). if a change of channels takes place, the settling time is 3 l/(output data rate) regardless of the sync input. the C3 db frequency is determined by the programmed first notch frequency according to the relationship: filter C3 db frequency = 0.262 first notch frequency.
2 C11C rev. e ad7712 tables i and ii show the output rms noise for some typical notch and C3 db frequencies. the numbers given are for the bipolar input ranges with a v ref of +2.5 v. these numbers are typical and are generated with an analog input voltage of 0 v. the output noise from the part comes from two sources. first, there is the electrical noise in the semiconductor devices used in the imple menta- tion of the modulator (device noise). secondly, when the analog input signal is converted into the digital domain, quantization noise is added. the device noise is at a low level and is largely independent of frequency. the quantization noise starts at an even lower level but rises rapidly with increasing frequency to become the dominant noise source. consequently, lower filter notch setting s (below 60 hz approximately) tend to be device noise dominated while higher notch settings are dominated by quantization noise. changing the filter notch and cutoff frequency in the quantization noise dominated region results in a more dramatic improvemen t in noise performance than it does in the device noise dominated region as shown in table i. furthermore, quantization noise is added after the pga, so effective resolution is independent of gain for the higher filter notch frequencies. meanwhile, device noise is added in the pga and, therefore, effective resolution suffers a little at high gains for lower notch frequencies. at the lower filter notch settings (below 60 hz), the no missing codes performance of the device is at the 24-bit level. at the higher settings, more codes will be missed until at 1 khz notch setting, no missing codes performance is only guaranteed to the 12-bit level. however, since the effective resolution of the part is 10.5 bits for this filter notch setting, this no missing codes performan ce should be more than adequate for all applications. the effective resolution of the device is defined as the ratio of the output rms noise to the input full scale. this does not r emain constant with increasing gain or with increasing bandwidth. table ii shows the same table as table i except that the output is now expressed in terms of effective resolution (the magnitude of the rms noise with respect to 2 v ref /gain, i.e., the input full scale). it is possible to do post filtering on the device to improve the output data rate for a given C3 db frequency and also to further reduce the output noise (see digital filtering section). table i. output noise vs. gain and first notch frequency first notch of typical output rms noise ( m v) filter and o/p C3 db gain of gain of gain of gain of gain of gain of gain of gain of data rate 1 frequency 1248163264128 10 hz 2 2.62 hz 1.0 0.78 0.48 0.33 0.25 0.25 0.25 0.25 25 hz 2 6.55 hz 1.8 1.1 0.63 0.5 0.44 0.41 0.38 0.38 30 hz 2 7.86 hz 2.5 1.31 0.84 0.57 0.46 0.43 0.4 0.4 50 hz 2 13.1 hz 4.33 2.06 1.2 0.64 0.54 0.46 0.46 0.46 60 hz 2 15.72 hz 5.28 2.36 1.33 0.87 0.63 0.62 0.6 0.56 100 hz 3 26.2 hz 13 6.4 3.7 1.8 1.1 0.9 0.65 0.65 250 hz 3 65.5 hz 130 75 25 12 7.5 4 2.7 1.7 500 hz 3 131 hz 0.6 10 3 0.26 10 3 140 70 35 25 15 8 1 khz 3 262 hz 3.1 10 3 1.6 10 3 0.7 10 3 0.29 10 3 180 120 70 40 notes 1 the default condition (after the internal power-on reset) for the first notch of filter is 60 hz. 2 for these filter notch frequencies, the output rms noise is primarily dominated by device noise and as a result is independent of the value of the reference voltage. therefore, increasing the reference voltage will give an increase in the effective resolution of the device (i.e., the ratio of the rms noise to the input full scale is increased since the output rms noise remains constant as the input full scale increases). 3 for these filter notch frequencies, the output rms noise is dominated by quantization noise and as a result is proportional to the value of the reference voltage. table ii. effective resolution vs. gain and first notch frequency first notch of effective resolution 1 (bits) filter and o/p C3 db gain of gain of gain of gain of gain of gain of gain of gain of data rate frequency 1248163264128 10 hz 2.62 hz 22.5 21.5 21.5 21 20.5 19.5 18.5 17.5 25 hz 6.55 hz 21.5 21 21 20 19.5 18.5 17.5 16.5 30 hz 7.86 hz 21 21 20.5 20 19.5 18.5 17.5 16.5 50 hz 13.1 hz 20 20 20 20 19 18.5 17.5 16.5 60 hz 15.72 hz 20 20 20 19.5 19 18 17 16 100 hz 26.2 hz 18.5 18.5 18.5 18.5 18 17.5 17 16 250 hz 65.5 hz 15 15.5 15.5 15.5 15.5 15.5 15 14.5 500 hz 131 hz 13 13 13 13 13 12.5 12.5 12.5 1 khz 262 hz 10.5 10.5 11 11 11 10.5 10 10 note 1 effective resolution is defined as the magnitude of the output rms noise with respect to the input full scale (i.e., 2 v ref /gain). the above table applies for a v ref of +2.5 v and resolution numbers are rounded to the nearest 0.5 lsb.
rev. e C12C ad7712 circuit description the ad7712 is a sigma-delta a/d converter with on-chip digital filtering, intended for the measurement of wide dynamic range, low frequency signals such as those in industrial control or pro- cess control applications. it contains a sigma-delta (or charge balancing) adc, a calibration microcontroller with on-chip static ram, a clock oscillator, a digital filter and a bidirectional serial communications port. the part contains two analog input channels, one programmable gain differential input and one programmable gain high level single-ended input. the gain range on both inputs is from 1 to 128. for the ain1 input, this means that the input can accept unipolar signals of between 0 mv to +20 mv and 0 mv to +2.5 v or bipolar signals in the range from 20 mv to 2.5 v when the reference input voltage equals +2.5 v. the input volt- age range for the ain2 input is 4 v ref /gain and is 10 v with the nominal reference of +2.5 v and a gain of 1. the input signal to the selected analog input channel is continuously sampled at a rate determined by the frequency of the master clock, mclk in, and the selected gain (see table iii). a charge balancing a/d converter (sigma-delta modulator) con- verts the sampled signal into a digital pulse train whose duty cycle contains the digital information. the programmable gain function on the analog input is also incorporated in this sigma- delta modulator with the input sampling frequency being modi- fied to give the higher gains. a sinc 3 digital low-pass filter processes the output of the sigma-delta modulator and updates the output register at a rate determined by the first notch fre- quency of this filter. the output data can be read from the serial port randomly or periodically at any rate up to the output regis- ter update rate. the first notch of this digital filter (and hence its C3 db frequency) can be programmed via an on-chip control register. the programmable range for this first notch frequency is from 9.76 hz to 1.028 khz, giving a programmable range for the C3 db frequency of 2.58 hz to 269 hz. the basic connection diagram for the part is shown in figure 3. this shows the ad7712 in the external clocking mode with both the av dd and dv dd pins of the ad7712 being driven from the analog +5 v supply. some applications will have separate sup- plies for both av dd and dv dd , and in some of these cases, the analog supply will exceed the +5 v digital supply (see power supplies and grounding section). ref in(+) ref out ain1(+) ain1(C) ain2 agnd dgnd mclk in mclk out mode sclk sdata ref in(C) v bias a0 differential analog input single-ended analog input analog ground digital ground data ready transmit (write) receive (read) serial data serial clock address input +5v ad7712 10 m f 0.1 m f analog +5v supply av dd dv dd dv dd v ss standby sync drdy tfs rfs 0.1 m f figure 3. basic connection diagram 1000 10 0.1 10 1000 10000 100 1 100 notch frequency C hz output noise C m v gain of 16 gain of 32 gain of 64 gain of 128 figure 2b. plot of output noise vs. gain and notch frequency (gains of 16 to 128) 10000 100 0.1 10 1000 10000 gain of 1 gain of 2 gain of 4 gain of 8 1000 10 1 100 notch frequency C hz output noise C m v figure 2a. plot of output noise vs. gain and notch frequency (gains of 1 to 8) figures 2a and 2b give information similar to that outlined in table i. in these plots, the output rms noise is shown for the f ull range of available cutoffs frequencies rather than for some typical cutoff frequencies as in tables i and ii. the numbers given in th ese plots are typical values at +25 c.
2 C13C rev. e ad7712 oversampling is fundamental to the operation of sigma-delta adcs. using the quantization noise formula for an adc: snr = ( 6.02 number of bits + 1.76) db, a 1-bit adc or comparator yields an snr of 7.78 db. the ad7712 samples the input signal at a frequency of 39 khz or greater (see table iii). as a result, the quantization noise is spread over a much wider frequency than that of the band of interest. the noise in the band of interest is reduced still further by analog filtering in the modulator loop, which shapes the quantization noise spectrum to move most of the noise energy to frequencies outside the bandwidth of interest. the noise perfor- mance is thus improved from this 1-bit level to the performance outlined in tables i and ii and in figure 2. the output of the comparator provides the digital input for the 1-bit dac, so that the system functions as a negative feedback loop that tries to minimize the difference signal. the digital data that represents the analog input voltage is contained in the duty cycle of the pulse train appearing at the output of the compara- tor. it can be retrieved as a parallel binary data word using a digital filter. sigma-delta adcs are generally described by the order of the analog low-pass filter. a simple example of a first order sigma- delta adc is shown in figure 5. this contains only a first order low-pass filter or integrator. it also illustrates the derivation of the alternative name for these devices: charge balancing adcs. v in differential amplifier comparator Cfs dac +fs figure 5. basic charge-balancing adc it consists of a differential amplifier (whose output is the differ- ence between the analog input and the output of a 1-bit dac), an integrator and a comparator. the term charge balancing, comes from the fact that this system is a negative feedback loop that tries to keep the net charge on the integrator capacitor at zero by balancing charge injected by the input voltage with charge injected by the 1-bit dac. when the analog input is zero, the only contribution to the integrator output comes from the 1-bit dac. for the net charge on the integrator capacitor to be zero, the dac output must spend half its time at +fs and half its time at Cfs. assuming ideal components, the duty cycle of the comparator will be 50%. when a positive analog input is applied, the output of the 1-bit dac must spend a larger proportion of the time at +fs, so the duty cycle of the comparator increases. when a negative input voltage is applied, the duty cycle decreases. the ad7712 uses a second-order sigma-delta modulator and a digital filter that provides a rolling average of the sampled out- put. after power-up, or if there is a step change in the input voltage, there is a settling time that must elapse before valid data is obtained. the ad7712 provides a number of calibration options which can be programmed via the on-chip control register. a calibra- tion cycle may be initiated at any time by writing to this control register. the part can perform self-calibration using the on-chip calibration microcontroller and sram to store calibration parameters. other system components may also be included in the calibration loop to remove offset and gain errors in the input channel using the system calibration mode. another option is a background calibration mode where the part continuously per- forms self-calibration and updates the calibration coefficients. once the part is in this mode, the user does not have to worry about issuing periodic calibration commands to the device or asking the device to recalibrate when there is a change in the ambient temperature or power supply voltage. the ad7712 gives the user access to the on-chip calibration registers allowing the microprocessor to read the devices cali- bration coefficients and also to write its own calibration coeffi- cients to the part from prestored values in e 2 prom. this gives the microprocessor much greater control over the ad7712s calibration procedure. it also means that the user can verify that the device has performed its calibration correctly by comparing the coefficients after calibration with prestored values in e 2 prom. the ad7712 can be operated in single supply systems provided that the analog input voltage on the ain1 input does not go more negative than C30 mv. for larger bipolar signals on the ain1 input, a v ss of C5 v is required by the part. for battery operation or low power systems, the ad7712 offers a standby mode (controlled by the standby pin) that reduces idle power consumption to typically 100 m w. theory of operation the general block diagram of a sigma-delta adc is shown in figure 4. it contains the following elements: 1. a sample-hold amplifier. 2. a differential amplifier or subtracter. 3. an analog low-pass filter. 4. a 1-bit a/d converter (comparator). 5. a 1-bit dac. 6. a digital low-pass filter. analog low-pass filter comparator digital data dac s/h amp digital filter figure 4. general sigma-delta adc in operation, the analog signal sample is fed to the subtracter, along with the output of the 1-bit dac. the filtered difference signal is fed to the comparator, whose output samples the differ- ence signal at a frequency many times that of the analog signal sampling frequency (oversampling).
rev. e C14C ad7712 0 C240 C180 C220 10 C200 0 C120 C160 C140 C100 C80 C60 C20 C40 60 50 40 30 20 frequency C hz gain C dbs figure 6. frequency response of ad7712 filter since the ad7712 contains this on-chip, low-pass filtering, there is a settling time associated with step function inputs, and data on the output will be invalid after a step change until the settling time has elapsed. the settling time depends upon the notch frequency chosen for the filter. the output data rate equates to this filter notch frequency, and the settling time of the filter to a full-scale step input is four times the output data period. in applications using both input channels, the settling time of the filter must be allowed to elapse before data from the second channel is accessed. post filtering the on-chip modulator provides samples at a 19.5 khz output rate. the on-chip digital filter decimates these samples to pro- vide data at an output rate that corresponds to the programmed first notch frequency of the filter. since the output data rate exceeds the nyquist criterion, the output rate for a given band- width will satisfy most application requirements. however, there may be some applications which require a higher data rate for a given bandwidth and noise performance. applications that need this higher data rate will require some post filtering follow- ing the digital filter of the ad7712. for example, if the required bandwidth is 7.86 hz but the required update rate is 100 hz, the data can be taken from the ad7712 at the 100 hz rate giving a C3 db bandwidth of 26.2 hz. post filtering can be applied to this to reduce the bandwidth and output noise, to the 7.86 hz bandwidth level, while maintaining an output rate of 100 hz. post filtering can also be used to reduce the output noise from the device for bandwidths below 2.62 hz. at a gain of 128, the output rms noise is 250 nv. this is essentially device noise or white noise, and since the input is chopped, the noise has a flat frequency response. by reducing the bandwidth below 2.62 hz, the noise in the resultant passband can be reduced. a reduction in bandwidth by a factor of two results in a ? 2 reduction in the output rms noise. this additional filtering will result in a longer settling time. input sample rate the modulator sample frequency for the device remains at f clk in /512 (19.5 khz @ f clk in = 10 mhz) regardless of the selected gain. however, gains greater than 1 are achieved by a combination of multiple input samples per modulator cycle and a scaling of the ratio of reference capacitor to input capacitor. as a result of the multiple sampling, the input sample rate of the device varies with the selected gain (see table iii). the effective input impedance is 1/c f s where c is the input sam- pling capacitance and f s is the input sample rate. table iii. input sampling frequency vs. gain gain input sampling frequency (f s ) 1f clk in /256 (39 khz @ f clk in = 10 mhz) 22 f clk in /256 (78 khz @ f clk in = 10 mhz) 44 f clk in /256 (156 khz @ f clk in = 10 mhz) 88 f clk in /256 (312 khz @ f clk in = 10 mhz) 16 8 f clk in /256 (312 khz @ f clk in = 10 mhz) 32 8 f clk in /256 (312 khz @ f clk in = 10 mhz) 64 8 f clk in /256 (312 khz @ f clk in = 10 mhz) 128 8 f clk in /256 (312 khz @ f clk in = 10 mhz) digital filtering the ad7712s digital filter behaves like a similar analog filter, with a few minor differences. first, since digital filtering occurs after the a-to-d conversion process, it can remove noise injected during the conversion process. analog filtering cannot do this. on the other hand, analog filtering can remove noise superim- posed on the analog signal before it reaches the adc. digital filtering cannot do this, and noise peaks riding on signals near full scale have the potential to saturate the analog modulator and digital filter, even though the average value of the signal is within limits. to alleviate this problem, the ad7712 has over- range headroom built into the sigma-delta modulator and digital filter which allows overrange excursions of 5% above the analog input range. if noise signals are larger than this, consideration should be given to analog input filtering, or to reducing the input channel voltage so that its full scale is half that of the analog input channel full scale. this will provide an overrange capability greater than 100% at the expense of reducing the dynamic range by 1 bit (50%). filter characteristics the cutoff frequency of the digital filter is determined by the value loaded to bits fs0 to fs11 in the control register. at the maximum clock frequency of 10 mhz, the minimum cutoff frequency of the filter is 2.58 hz while the maximum program- mable cutoff frequency is 269 hz. figure 6 shows the filter frequency response for a cutoff fre- quency of 2.62 hz, which corresponds to a first filter notch frequency of 10 hz. this is a (sinx/x) 3 response (also called sinc 3 ) that provides >100 db of 50 hz and 60 hz rejection. programming a different cutoff frequency via fs0Cfs11 does not alter the profile of the filter response; it changes the fre- quency of the notches as outlined in the control register section.
2 C15C rev. e ad7712 table iv. typical external series resistance that will not introduce 16-bit gain error external capacitance (pf) gain 0 50 100 500 1000 5000 1 184 k w 45.3 k w 27.1 k w 7.3 k w 4.1 k w 1.1 k w 2 88.6 k w 22.1 k w 13.2 k w 3.6 k w 2.0 k w 560 w 4 41.4 k w 10.6 k w 6.3 k w 1.7 k w 970 w 270 w 8C128 17.6 k w 4.8 k w 2.9 k w 790 w 440 w 120 w table v. typical external series resistance that will not introduce 20-bit gain error external capacitance (pf) gain 0 50 100 500 1000 5000 1 145 k w 34.5 k w 20.4 k w 5.2 k w 2.8 k w 700 w 2 70.5 k w 16.9 k w 10 k w 2.5 k w 1.4 k w 350 w 4 31.8 k w 8.0 k w 4.8 k w 1.2 k w 670 w 170 w 8C128 13.4 k w 3.6 k w 2.2 k w 550 w 300 w 80 w the numbers in the above tables assume a full-scale change on the analog input. in any case, the error introduced due to longer charging times is a gain error which can be removed using the system calibration capabilities of the ad7712 provided that the resultant span is within the span limits of the system calibration techniques for the ad7712. the ain2 input contains a resistive attenuation network as outlined in figure 8. the typical input impedance on this input is 44 k w . as a result, the ain2 input should be driven from a low impedance source. 33k v v bias ain2 11k v modulator circuit figure 8. ain2 input impedance antialias considerations the digital filter does not provide any rejection at integer mul- tiples of the modulator sample frequency (n 19.5 khz, where n = 1, 2, 3 . . . ). this means that there are frequency bands, f 3 db wide (f 3 db is cutoff frequency selected by fs0 to fs11) where noise passes unattenuated to the output. however, due to the ad7712s high oversampling ratio, these bands occupy only a small fraction of the spectrum and most broadband noise is filtered. in any case, because of the high oversampling ratio a simple, rc, single pole filter is generally sufficient to attenuate the signals in these bands on the analog input and thus provide adequate antialiasing filtering. if passive components are placed in front of the ain1 input of the ad7712, care must be taken to ensure that the source imped- ance is low enough so as not to introduce gain errors in the sys- tem. the dc input impedance for the ain1 input is over 1 g w . the input appears as a dynamic load that varies with the clock frequency and with the selected gain (see figure 7). the input sample rate, as shown in table iii, determines the time allowed for the analog input capacitor, c in , to be charged. external impedances result in a longer charge time for this capacitor, and this may result in gain errors being introduced on the analog inputs. table iv shows the allowable external resistance/ capacitance values such that no gain error to the 16-bit level is introduced while table v shows the allowable exte rnal resistance/capacitance values such that no gain error to the 20-bit level is introduced. both inputs of the differ ential input channels (ain1) look into similar input circuitry. r int (7k v typ) c int (11.5pf typ) v bias ain switching frequency depends on f clkin and selected gain high impedance >1g v figure 7. ain1 input impedance
rev. e C16C ad7712 to 1 ma to an external load. in applications where ref out is connected directly to ref in(+), ref in(C) should be tied to agnd to provide the nominal +2.5 v reference for the ad7712. the reference inputs of the ad7712, ref in(+) and ref in(C), provide a differential reference input capability. the common-mode range for these differential inputs is from v ss to av dd . the nominal differential voltage, v ref (ref in(+) C ref in(C)), is +2.5 v for specified operation, but the reference voltage can go to +5 v with no degradation in performance provided that the absolute value of ref in(+) and ref in(C) does not exceed its av dd and v ss limits and the v bias input voltage range limits are obeyed. the part is also functional with v ref voltages down to 1 v but with degraded performance as the output noise will, in terms of lsb size, be larger. ref in(+) must always be greater than ref in(C) for correct opera- tion of the ad7712. both reference inputs provide a high impedance, dynamic load similar to the ain1 analog inputs. the maximum dc input leakage current is 10 pa ( 1 na over temperature) and source resistance may result in gain errors on the part. the reference inputs look like the ain1 analog input (see figure 7). in this case, r int is 5 k w typ and c int varies with gain. the input sample rate is f clk in /256 and does not vary with gain. for gains of 1 to 8 c int is 20 pf; for a gain of 16 it is 10 pf; for a gain of 32 it is 5 pf; for a gain of 64 it is 2.5 pf; and for a gain of 128 it is 1.25 pf. the digital filter of the ad7712 removes noise from the refer- ence input just as it does with the analog input, and the same limitations apply regarding lack of noise rejection at integer multiples of the sampling frequency. the output noise perfor- mance outlined in tables i and ii assumes a clean reference. if the reference noise in the bandwidth of interest is excessive, it can degrade the performance of the ad7712. using the on-chip reference as the reference source for the part (i.e., connecting ref out to ref in) results in somewhat degraded output noise performance from the ad7712 for portions of the noise table t hat are dom inated by the device noise. the on-chip refer- ence noise effect is eliminated in ratiometric applications where the reference is used to provide its excitation voltage for the analog front end. the connection scheme shown in figure 9 between the ref out and ref in pins of the ad7712 is rec- ommended when using the on-chip reference. recommended reference voltage sources for the ad7712 include the ad780 and ad680 2.5 v references. ref out ref in(+) ad7712 ref in(C) figure 9. ref out/ref in connection analog input functions analog input ranges the analog inputs on the ad7712 provide the user with consid- erable flexibility in terms of analog input voltage ranges. one of the inputs is a differential, programmable gain, input channel which can handle either unipolar or bipolar input signals. the common-mode range of this input is from v ss to av dd provided that the absolute value of the analog input voltage lies between v ss C 30 mv and av dd + 30 mv. the second analog input is a single-ended, programmable gain, high level input that accepts analog input ranges of 0 to +4 v ref /gain or 4 v ref /gain. the dc input leakage current on the ain1 input is 10 pa maxi- mum at 25 c ( 1 na over temperature). this results in a dc offset voltage developed across the source impedance. however, this dc offset effect can be compensated for by a combination of the differential input capability of the part and its system cali- bration mode. the dc input current on the ain2 input depends on the input voltage. for the nominal input voltage range of 10 v, the input current is 225 m a typ. burnout current the ain1(+) input of the ad7712 contains a 4.5 m a current source that can be turned on/off via the control register. this current source can be used in checking that a transducer has not burned out or gone open circuit before attempting to take mea- surements on that channel. if the current is turned on and is allowed flow into the transducer and a measurement of the input voltage on the ain1 input is taken, it can indicate that the transducer is not functioning correctly. for normal operation, this burnout current is turned off by writing a 0 to the bo bit in the control register. bipolar/unipolar inputs the two analog inputs on the ad7712 can accept either unipo- lar or bipolar input voltage ranges. bipolar or unipolar options are chosen by programming the b/u bit of the control register. this programs both channels for either unipolar or bipolar operation. programming the part for either unipolar or bipolar operation does not change any of the input signal conditioning; it simply changes the data output coding. the data coding is binary for unipolar inputs and offset binary for bipolar inputs. the ain1 input channel is differential and, as a result, the voltage to which the unipolar and bipolar signals are referenced is the voltage on the ain1(C) input. for example, if ain1(C) is +1.25 v and the ad7712 is configured for unipolar operation with a gain of 1 and a v ref of +2.5 v, the input voltage range on the ain1(+) input is +1.25 v to +3.75 v. if ain1(C) is +1.25 v and the ad7712 is configured for bipolar mode with a gain of 1 and a v ref of +2.5 v, the analog input range on the ain1(+) input is C1.25 v to +3.75 v. for the ain2 input, the input signals are referenced to agnd. reference input/output the ad7712 contains a temperature compensated +2.5 v refer- ence which has an initial tolerance of 1%. this reference volt- age is provided at the ref out, pin and it can be used as the reference voltage for the part by connecting the ref out pin to the ref in(+) pin. this ref out pin is a single-ended output, referenced to agnd, which is capable of providing up
2 C17C rev. e ad7712 the current drawn from the dv dd power supply is also directly related to f clk in . reducing f clk in by a factor of two will halve the dv dd current but will not affect the current drawn from the av dd power supply. system synchronization if multiple ad7712s are operated from a common master clock, they can be synchronized to update their output registers simul- taneously. a falling edge on the sync input resets the filter and places the ad7712 into a consistent, known state. a com- mon signal to the ad7712s sync inputs will synchronize their operation. this would normally be done after each ad7712 has performed its own calibration or has had calibration coefficients loaded to it. the sync input can also be used to reset the digital filter in systems where the turn-on time of the digital power supply (dv dd ) is very long. in such cases, the ad7712 will start oper- ating internally before the dv dd line has reached its minimum operating level, +4.75 v. with a low dv dd voltage, the ad7712s internal digital filter logic does not operate correctly. thus, the ad7712 may have clocked itself into an incorrect operating condition by the time that dv dd has reached its cor- rect level. the digital filter will be reset upon issue of a calibra- tion command (whether it is self-calibration, system calibration or background calibration) to the ad7712. this ensures correct operation of the ad7712. in systems where the power-on de- fault conditions of the ad7712 are acceptable, and no calibra- tion is performed after power-on, issuing a sync pulse to the ad7712 will reset the ad7712s digital filter logic. an r, c on the sync line, with r, c time constant longer than the dv dd power-on time, will perform the sync function. accuracy sigma-delta adcs, like vfcs and other integrating adcs, do not contain any source of nonmonotonicity and inherently offer no missing codes performance. the ad7712 achieves excellent linearity by the use of high quality, on-chip silicon dioxide ca- pacitors, which have a very low capacitance/voltage coefficient. the device also achieves low input drift through the use of chopper stabilized techniques in its input stage. to ensure excellent performance over time and temperature, the ad7712 uses digital calibration techniques that minimize offset and gain error. autocalibration autocalibration on the ad7712 removes offset and gain errors from the device. a calibration routine should be initiated on the device whenever there is a change in the ambient operating temperature or supply voltage. it should also be initiated if there is a change in the selected gain, filter notch or bipolar/unipolar input range. however, if the ad7712 is in its background cali- bration mode, the above changes are all automatically taken care of (after the settling time of the filter has been allowed for). the ad7712 offers self-calibration, system calibration and background calibration facilities. for calibration to occur on the selected channel, the on-chip microcontroller must record the modulator output for two different input conditions. these are zero-scale and full-scale points. with these readings, the microcontroller can calculate the gain slope for the input to output transfer function of the converter. internally, the part works with a resolution of 33 bits to determine its conversion result of either 16 bits or 24 bits. v bias input the v bias input determines at what voltage the internal analog circuitry is biased. it essentially provides the return path for analog currents flowing in the modulator, and as such it should be driven from a low impedance point to minimize errors. for maximum internal headroom, the v bias voltage should be set halfway between av dd and v ss . the difference between av dd and (v bias + 0.85 v ref ) determines the amount of headroom the circuit has at the upper end, while the difference between v ss and (v bias C 0.85 v ref ) determines the amount of headroom the circuit has at the lower end. care should be taken in choosing a v bias voltage to ensure that it stays within prescribed limits. for single +5 v operation, the selected v bias voltage must ensure that v bias 0.85 v ref does not exceed av dd or v ss or that the v bias voltage itself is greater than v ss + 2.1 v and less than av dd C 2.1 v. for single +10 v operation or dual 5 v operation, the selected v bias voltage must ensure that v bias 0.85 v ref does not exceed av dd or v ss or that the v bias voltage itself is greater than v ss + 3 v or less than av dd C 3 v. for example, with av dd = +4.75 v, v ss = 0 v and v ref = +2.5 v, the allowable range for the v bias voltage is +2.125 v to +2.625 v. with av dd = +9.5 v, v ss = 0 v and v ref = +5 v, the range for v bias is +4.25 v to +5.25 v. with av dd = +4.75 v, v ss = C4.75 v and v ref = +2.5 v, the v bias range is C2.625 v to +2.625 v. the v bias voltage does have an effect on the av dd power sup- ply rejection performance of the ad7712. if the v bias voltage tracks the av dd supply, it improves the power supply rejection from the av dd supply line from 80 db to 95 db. using an ex- ternal zener diode, connected between the av dd line and v bias, as the source for the v bias voltage gives the improvement in av dd power supply rejection performance. using the ad7712 system design considerations the ad7712 operates differently from successive approximation adcs or integrating adcs. since it samples the signal continu- ously, like a tracking adc, there is no need for a start convert command. the output register is updated at a rate determined by the first notch of the filter and the output can be read at any time, either synchronously or asynchronously. clocking the ad7712 requires a master clock input, which may be an external ttl/cmos compatible clock signal applied to the mclk in pin with the mclk out pin left unconnected. alternatively, a crystal of the correct frequency can be con- nected between mclk in and mclk out, in which case the clock circuit will function as a crystal controlled oscillator. for lower clock frequencies, a ceramic resonator may be used in- stead of the crystal. for these lower frequency oscillators, exter- nal capacitors may be required on either the ceramic resonator or on the crystal. the input sampling frequency, the modulator sampling fre- quency, the C3 db frequency, output update rate and calibration time are all directly related to the master clock frequency, f clk in. reducing the master clock frequency by a factor of two will halve the above frequencies and update rate and will double the calibration time.
rev. e C18C ad7712 unipo lar mode, the system calibration is performed between the two endpoints of the transfer function; in the bipolar mode, it is performed between midscale and positive full scale. this two-step system calibration mode offers another feature. after the sequence has been completed, additional offset or gain calibrations can be performed by themselves to adjust the zero reference point or the system gain. this is achieved by perform- ing the first step of the system calibration sequence (by writing 0, 1, 0 to md2, md1, md0). this will adjust the zero-scale or offset point but will not change the slope factor from what was set during a full system calibration sequence. system calibration can also be used to remove any errors from an antialiasing filter on the analog input. a simple r, c anti- aliasing filter on the front end may introduce a gain error on the analog input voltage but the system calibration can be used to remove this error. system offset calibration system offset calibration is a variation of both the system cali- bration and self-calibration. in this case, the zero-scale point for the system is presented to the ain input of the converter. system offset calibration is initiated by writing 1, 0, 0 to md2, md1, md0. the system zero-scale coefficient is determined by converting the voltage applied to the ain input, while the full- scale coefficient is determined from the span between this ain conversion and a conversion on v ref . the zero-scale point should be applied to the ain input for the duration of the cali- bration sequence. this is a one-step calibration sequence with drdy going low when the sequence is completed. in the uni- polar mode, the system offset calibration is performed between the two endpoints of the transfer function; in the bipolar mode, it is performed between midscale and positive full scale. background calibration the ad7712 also offers a background calibration mode where the part interleaves its calibration procedure with its normal conversion sequence. in the background calibration mode, the same voltages are used as the calibration points as are used in the self-calibration mode, i.e., shorted inputs and v ref . the background calibration mode is invoked by writing 1, 0, 1 to md2, md1, md0 of the control register. when invoked, the background calibration mode reduces the output data rate of the ad7712 by a factor of six while the C3 db bandwidth remains unchanged. its advantage is that the part is continually perform- ing calibration and automatically updating its calibration coeffi- cients. as a result, the effects of temperature drift, supply sensitivity and time drift on zero- and full-scale errors are auto- matically removed. when the background calibration mode is turned on, the part will remain in this mode until bits md2, md1 and md0 of the control register are changed. with back- ground calibration mode on, the first result from the ad7712 will be incorrect as the full-scale calibration will not have been performed. for a step change on the input, the second output update will have settled to 100% of the final value. table vi summarizes the calibration modes and the calibration points associated with them. it also gives the duration from when the calibration is invoked to when valid data is available to the user. the ad7712 also provides the facility to write to the on-chip calibration registers, and in this manner the span and offset for the part can be adjusted by the user. the offset calibration regis- ter contains a value which is subtracted from all conversion results, while the full-scale calibration register contains a value which is multiplied by all conversion results. the offset calibra- tion coefficient is subtracted from the result prior to the multi- plication by the full-scale coefficient. in the first three modes outlined here, the drdy line indicates that calibration is com- plete by going low. if drdy is low before (or goes low during) the calibration command, it may take up to one modulator cycle before drdy goes high to indicate that calibration is in progress. therefore, the drdy line should be ignored for up to one modulator cycle after the last bit of the calibration com- mand is written to the control register. self-calibration in the self-calibration mode with a unipolar input range, the zero-scale point used in determining the calibration coefficients is with both inputs shorted (i.e., ain1(+) = ain1(C) = v bias for ain1 and ain2 = v bias for ain2 ) and the full-scale point is v ref . the zero-scale coefficient is determined by con- verting an internal shorted inputs node. the full-scale coeffi- cient is determined from the span between this shorted inputs conversion and a conversion on an internal v ref node. the self- calibration mode is invoked by writing the appropriate values (0, 0, 1) to the md2, md1 and md0 bits of the control register. in this calibration mode, the shorted inputs node is switched in to the modulator first and a conversion is performed; the v ref node is then switched in, and another conversion is performed. when the calibration sequence is complete, the calibration coefficients updated and the filter resettled to the analog input voltage, the drdy output goes low. the self-calibration proce- dure takes into account the selected gain on the pga. for bipolar input ranges in the self-calibrating mode, the sequence is very similar to that just outlined. in this case, the two points that the ad7712 calibrates are midscale (bipolar zero) and positive full scale. system calibration system calibration allows the ad7712 to compensate for system gain and offset errors as well as its own internal errors. system calibration performs the same slope factor calculations as self- calibration but uses voltage values presented by the system to the ain inputs for the zero and full-scale points. system cali- bration is a two-step process. the zero-scale point must be presented to the converter first. it must be applied to the con- verter before the calibration step is initiated and remain stable until the step is complete. system calibration is initiated by writing the appropriate values (0, 1, 0) to the md2, md1 and md0 bits of the control register. the drdy output from the device will signal when the step is complete by going low. after the zero-scale point is calibrated, the full-scale point is applied and the second step of the calibration process is initiated by again writing the appropriate values (0, 1, 1) to md2, md1 and md0. again the full-scale voltage must be set up before the calibration is initiated, and it must remain stable throughout the calibration step. drdy goes low at the end of this second step to indicate that the system calibration is complete. in the
2 C19C rev. e ad7712 table vi. calibration truth table cal type md2, md1, md0 zero-scale cal full-scale cal sequence duration self-cal 0, 0, 1 shorted inputs v ref one step 9 1/output rate system cal 0, 1, 0 ain C two step 4 1/output rate system cal 0, 1, 1 C ain two step 4 1/output rate system offset cal 1, 0, 0 ain v ref one step 9 1/output rate background cal 1, 0, 1 shorted inputs v ref one step 6 1/output rate measurement errors due to offset drift or gain drift can be elimi- nated at any time by recalibrating the converter or by operating the part in the background calibration mode. using the system calibration mode can also minimize offset and gain errors in the signal conditioning circuitry. integral and differential linearity errors are not significantly affected by temperature changes. power supplies and grounding since the analog inputs and reference input are differential, most of the voltages in the analog modulator are common-mode voltages. v bias provides the return path for most of the analog currents flowing in the analog modulator. as a result, the v bias input should be driven from a low impedance to minimize errors due to charging/discharging impedances on this line. when the internal reference is used as the reference source for the part, agnd is the ground return for this reference voltage. the analog and digital supplies to the ad7712 are independent and separately pinned out to minimize coupling between the analog and digital sections of the device. the digital filter will provide rejection of broadband noise on the power supplies, except at integer m ultiples of the modulator sampling frequency. the digital supply (dv dd ) must not exceed the analog positive supply (av dd ) by more than 0.3 v in normal operation. if sepa- rate analog and digital supplies are used, the recommended decoupling scheme is shown in figure 10. in systems where av dd = +5 v and dv dd = +5 v, it is recommended that av dd and dv dd are driven from the same +5 v supply, although each supply should be decoupled separately as shown in figure 10. it is preferable that the common supply is the systems a nalog +5 v supply. it is also important that power is applied to the ad7712 before signals at ref in, ain or the logic input pins in order to avoid excessive current. if separate supplies are used for the ad7712 and the system digital circuitry, then the ad7712 should be powered up first. if it is not possible to guarantee this, then current limiting resistors should be placed in series with the logic inputs. ad7712 0.1 m f 0.1 m f 10 m f analog supply digital +5v supply av dd dv dd figure 10. recommended decoupling scheme span and offset limits whenever a system calibration mode is used, there are limits on the amount of offset and span that can be accommodated. the range of input span in both the unipolar and bipolar modes for ain1 has a minimum value of 0.8 v ref /gain and a maxi- mum value of 2.1 v ref /gain. for ain2, both numbers are a factor of four higher. the amount of offset which can be accommodated depends on whether the unipolar or bipolar mode is being used. this offset range is limited by the requirement that the positive full-scale calibration limit is 1.05 v ref /gain for ain1. therefore, the offset range plus the span range cannot exceed 1.05 v ref / gain for ain1. if the span is at its minimum (0.8 v ref / gain) the maximum the offset can be is (0.25 v ref /gain) for ain1. for ain2, both ranges are multiplied by a factor of four. in the bipolar mode, the system offset calibration range is again restricted by the span range. the span range of the converter in bipolar mode is equi distant around the voltage used for the zero- scale point, thus the offset range plus half the span range cannot exceed (1.05 v ref /gain) for ain1. if the span is set to 2 v ref /gain, the offset span cannot move more than (0.05 v ref /gain) before the endpoints of the transfer function ex- ceed the input overrange limits (1.05 v ref /gain) for ain1. if the span range is set to the minimum (0.4 v ref /gain), the maximum allowable offset range is (0.65 v ref /gain) for ain1. once again, for ain2, both ranges are multiplied by a factor of four. power-up and calibration on power-up, the ad7712 performs an internal reset which sets the contents of the control register to a known state. however, to ensure correct calibration for the device a calibration routine should be performed after power-up. the power dissipation and temperature drift of the ad7712 are low and no warm-up time is required before the initial calibra- tion is performed. however, if an external reference is being used, this reference must have stabilized before calibration is initiated. drift considerations the ad7712 uses chopper stabilization techniques to minimize input offset drift. charge injection in the analog switches and dc leakage currents at the sampling node are the primary sources of offset voltage drift in the converter. the dc input leakage cur- rent is essentially independent of the selected gain. gain drift within the converter depends primarily upon the temperature tracking of the internal capacitors. it is not affected by leakage currents.
rev. e C20C ad7712 the output data register. it is reset high when the last bit of data (either 16th bit or 24th bit) is read from the output register. if data is not read from the output register, the drdy line will remain low. the output register will continue to be updated at the output update rate but drdy will not indicate this. a read from the device in this circumstance will access the most recent word in the output register. if a new data word becomes avail- able to the output register while data is being read from the output register, drdy will not indicate this and the new data word will be lost to the user. drdy is not affected by reading from the control register or the calibration registers. data can only be accessed from the output data register when drdy is low. if rfs goes low with drdy high, no data trans- fer will take place. drdy does not have any effect on reading data from the control register or from the calibration registers. figure 11 shows a timing diagram for reading from the ad7712 in the self-clocking mode. this read operation shows a read from the ad7712s output data register. a read from the con- trol register or calibration registers is similar, but in these cases the drdy line is not related to the read function. depending on the output update rate, it can go low at any stage in the control/calibration register read cycle without affecting the read and its status should be ignored. a read operation from either the control or calibration registers must always read 24 bits of data from the respective register. figure 11 shows a read operation from the ad7712. for the timing diagram shown, it is assumed that there is a pull-up resistor on the sclk output. with drdy low, the rfs input is brought low. rfs going low enables the serial clock of the ad7712 and also places the msb of the word on the serial data line. all subsequent data bits are clocked out on a high to low transition of the serial clock and are valid prior to the following rising edge of this clock. the final active falling edge of sclk clocks out the lsb, and this lsb is valid prior to the final ac- tive rising edge of sclk. coincident with the next falling edge of sclk, drdy is reset high. drdy going high turns off the sclk and the sdata outputs. this means that the data hold time for the lsb is slightly shorter than for all other bits. sdata (o) sclk (o) three-state rfs (i) a0 (i) drdy (o) msb lsb t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 10 figure 11. self-clocking mode, output data read operation digital interface the ad7712s serial communications port provides a flexible arrangement to allow easy interfacing to industry-standard microprocessors, microcontrollers and digital signal processors. a serial read to the ad7712 can access data from the output register, the control register or from the calibration registers. a serial write to the ad7712 can write data to the control register or the calibration registers. two different modes of operation are available, optimized for different types of interface where the ad7712 can act either as master in the system (it provides the serial clock) or as slave (an external serial clock can be provided to the ad7712). these two modes, labelled self-clocking mode and external clocking mode, are discussed in detail in the following sections. self-clocking mode the ad7712 is configured for its self-clocking mode by tying the mode pin high. in this mode, the ad7712 provides the serial clock signal used for the transfer of data to and from the ad7712. this self-clocking mode can be used with processors that allow an external device to clock their serial port including most digital signal processors and microcontrollers such as the 68hc11 and 68hc05. it also allows easy interfacing to serial parallel conversion circuits in systems with parallel data commu- nication, allowing interfacing to 74xx299 universal shift regis- ters without any additional decoding. in the case of shift registers, the serial clock line should have a pull-down resistor instead of the pull-up resistor shown in figure 11 and figure 12. read operation data can be read from either the output register, the control register or the calibration registers. a0 determines whether the data read accesses data from the control register or from the output/calibration registers. this a0 signal must remain valid for the duration of the serial read operation. with a0 high, data is accessed from either the output register or from the calibra- tion registers. with a0 low, data is accessed from the control register. the function of the drdy line is dependent only on the output update rate of the device and the reading of the output data register. drdy goes low when a new data word is available in
2 C21C rev. e ad7712 write operation data can be written to either the control register or calibration registers. in either case, the write operation is not affected by the drdy line and the write operation does not have any effect on the status of drdy . a write operation to the control register or the calibration register must always write 24 bits to the respective register. figure 12 shows a write operation to the ad7712. a0 deter- mines whether a write operation transfers data to the control register or to the calibration registers. this a0 signal must remain valid for the duration of the serial write operation. the falling edge of tfs enables the internally generated sclk output. the serial data to be loaded to the ad7712 must be valid on the rising edge of this sclk signal. data is clocked into the ad7712 on the rising edge of the sclk signal with the msb transferred first. on the last active high time of sclk, the lsb is loaded to the ad7712. subsequent to the next falling edge of sclk, the sclk output is turned off. (the timing diagram of figure 12 assumes a pull-up resistor on the sclk line.) external clocking mode the ad7712 is configured for its external clocking mode by tying the mode pin low. in this mode, sclk of the ad7712 is configured as an input, and an external serial clock must be provided to this sclk pin. this external clocking mode is designed for direct interface to systems which provide a serial clock output which is synchronized to the serial data output, including microcontrollers such as the 80c51, 87c51, 68hc11 and 68hc05 and most digital signal processors. read operation as with the self-clocking mode, data can be read from either the output register, the control register or the calibration registers. a0 determines whether the data read accesses data from the control register or from the output/calibration registers. this a0 signal must remain valid for the duration of the serial read operation. with a0 high, data is accessed from either the output register or from the calibration registers. with a0 low, data is accessed from the control register. the function of the drdy line is dependent only on the output update rate of the device and the reading of the output data register. drdy goes low when a new data word is available in the output data register. it is reset high when the last bit of data (either 16th bit or 24th bit) is read from the output register. if data is not read from the output register, the drdy line will remain low. the output register will continue to be updated at the output update rate, but drdy will not indicate this. a read from the device in this circumstance will access the most recent word in the output register. if a new data word becomes avail- able to the output register while data is being read from the output register, drdy will not indicate this and the new data word will be lost to the user. drdy is not affected by reading from the control register or the calibration register. data can only be accessed from the output data register when drdy is low. if rfs goes low while drdy is high, no data tran sfer will take place. drdy does not have any effect on reading data from the control register or from the calibration registers. figures 13a and 13b show timing diagrams for reading from the ad7712 in the external clocking mode. figure 13a shows a situation where all the data is read from the ad7712 in one read operation. figure 13b shows a situation where the data is read from the ad7712 over a number of read operations. both read operations show a read from the ad7712s output data register. a read from the control register or c alibration registers is sim ilar, but in these cases the drdy line is not related to the read func- tion. depending on the output update rate, it can go low at any stage in the control/calibration register read cycle without affect- ing the read and its status should be ignored. a read operation from either the control or calibration registers must always read 24 bits of data from the respective register. sdata (o) sclk (o) tfs (i) a0 (i) msb lsb t 15 t 16 t 17 t 18 t 19 t 14 t 9 t 10 figure 12. self-clocking mode, control/calibration register write operation
rev. e C22C ad7712 figure 13a shows a read operation from the ad7712 where rfs remains low for the duration of the data word transmission. with drdy low, the rfs input is brought low. the input sclk signal should be low between read and write operations. rfs going low places the msb of the word to be read on the serial data line. all subsequent data bits are clocked out on a high to low transition of the serial clock and are valid prior to the following rising edge of this clock. the penultimate falling edge of sclk clocks out the lsb and the final falling edge resets the drdy line high. this rising edge of drdy turns off the serial data output. figure 13b shows a timing diagram for a read operation where rfs returns high during the transmission of the word and re- turns low again to access the rest of the data word. timing parameters and functions are very similar to that outlined for figure 13a, but figure 13b has a number of additional times to show timing relationships when rfs returns high in the middle of transferring a word. rfs should return high during a low time of sclk. on the rising edge of rfs , the sdata output is turned off. drdy remains low and will remain low until all bits of the data word are read from the ad7712, regardless of the number of times rfs changes state during the read operation. depending on the time between the falling edge of sclk and the rising edge of rfs , the next bit (bit n + 1) may appear on the databus be- fore rfs goes high. when rfs returns low again, it activates the sdata output. when the entire word is transmitted, the drdy line will go high, turning off the sdata output as per figure 13a. rfs (i) sclk (i) sdata (o) lsb msb three-state a0 (i) drdy (o) t 20 t 21 t 22 t 23 t 24 t 25 t 26 t 27 t 28 t 29 figure 13a. external clocking mode, output data read operation three-state msb bit n bit n+1 sdata (o) sclk (i) rfs (i) a0 (i) drdy (o) t 20 t 22 t 26 t 24 t 25 t 27 t 31 t 24 t 25 t 30 figure 13b. external clocking mode, output data read operation ( rfs returns high during read operation)
2 C23C rev. e ad7712 write operation data can be written to either the control register or calibration registers. in either case, the write operation is not affected by the drdy line, and the write operation does not have any effect on the status of drdy . a write operation to the control regis- ter or the calibration register must always write 24 bits to the respective register. figure 14a shows a write operation to the ad7712 with tfs remaining low for the duration of the write operation. a0 deter- mines whether a write operation transfers data to the control register or to the calibration registers. this a0 signal must remain valid for the duration of the serial write operation. as before, the serial clock line should be low between read and write operations. the serial data to be loaded to the ad7712 must be valid on the high level of the externally applied sclk signal. data is clocked into the ad7712 on the high level of this sclk signal with the msb transferred first. on the last active high time of sclk, the lsb is loaded to the ad7712. figure 14b shows a timing diagram for a write operation to the ad7712 with tfs returning high during the write operation and returning low again to write the rest of the data word. tim- ing parameters and functions are very similar to that outlined for figure 14a, but figure 14b has a number of additional times to show timing relationships when tfs returns high in the middle of transferring a word. data to be loaded to the ad7712 must be valid prior to the rising edge of the sclk signal. tfs should return high during the low time of sclk. after tfs returns low again, the next bit of the data word to be loaded to the ad7712 is clocked in on next high level of the sclk input. on the last active high time of the sclk input, the lsb is loaded to the ad7712. sclk (i) sdata (i) tfs (i) a0 (i) msb lsb t 32 t 33 t 26 t 27 t 35 t 36 t 34 figure 14a. external clocking mode, control/calibration register write operation sclk (i) sdata (i) tfs (i) a0 (i) msb bit n bit n+1 t 32 t 26 t 30 t 35 t 27 t 36 t 35 t 36 figure 14b. external clocking mode, control/calibration register write operation ( tfs returns high during write operation)
rev. e C24C ad7712 no yes bring rfs low 3 3 reverse order of bits bring rfs high poll drdy configure & initialize m c/ m p serial port drdy low? bring rfs , tfs high read serial buffer start figure 16. flowchart for continuous read operations to the ad7712 the flowchart for figure 17 is for a single 24-bit write operation to the ad7712 control or calibration registers. this shows data being transferred from data memory to the accumulator before being written to the serial buffer. some microprocessor systems will allow data to be written directly to the serial buffer from data memory. the writing of data to the serial buffer from the accumulator will generally consist of either two or three write operations, depending on the size of the serial buffer. the flowchart also shows the option of the bits being reversed before being written to the serial buffer. this depends on whether the first bit transmitted by the microprocessor is the msb or the lsb. the ad7712 expects the msb as the first bit in the data stream. in cases where the data is being read or being written in bytes and the data has to be reversed, the bits will have to be reversed for every byte. simplifying the external clocking mode interface in many applications, the user may not require the facility of writing to the on-chip calibration registers. in this case, the serial interface to the ad7712 in external clocking mode can be simplified by connecting the tfs line to the a0 input of the ad7712 (see figure 15). this means that any write to the de- vice will load data to the control register (since a0 is low while tfs is low) and any read to the device will access data from the output data register or from the calibration registers (since a0 is high while rfs is low). it should be noted that in this arrange- ment the user does not have the capability of reading from the control register. ad7712 sdata sclk tfs a0 four inter- face lines rfs figure 15. simplified interface with tfs connected to a0 another method of simplifying the interface is to generate the tfs signal from an inverted rfs signal. however, generating the signals the opposite way around ( rfs from an inverted tfs ) will cause writing errors. microcomputer/microprocessor interfacing the ad7712s flexible serial interface allows for easy interface to most microcomputers and microprocessors. figure 16 shows a flowchart diagram for a typical programming sequence for reading data from the ad7712 to a microcomputer while figure 17 shows a flowchart diagram for writing data to the ad7712. figures 18, 19 and 20 show some typical interface circuits. the flowchart of figure 16 is for continuous read operations from the ad7712 output register. in the example shown, the drdy line is continuously polled. depending on the micropro- cessor configuration, the drdy line may come to an interrupt input in which case the drdy will automatically generate an interrupt without being polled. the reading of the serial buffer could be anything from one read operation up to three read operations (where 24 bits of data are read into an 8-bit serial register). a read operation to the control/calibration registers is similar, but in this case the status of drdy can be ignored. the a0 line is brought low when the rfs line is brought low when reading from the control register. the flowchart also shows the bits being reversed after they have been read in from the serial port. this depends on whether the microprocessor expects the msb of the word first or the lsb of the word first. the ad7712 outputs the msb first.
2 C25C rev. e ad7712 reverse order of bits start write data from accumulator to serial buffer bring tfs & a0 low load data from address to accumulator configure & initialize m c/ m p serial port bring rfs , tfs & a0 high bring tfs & a0 high end 3 3 figure 17. flowchart for single write operation to the ad7712 ad7712 to 8051 interface figure 18 shows an interface between the ad7712 and the 8xc51 microcontroller. the ad7712 is configured for its exter- nal clocking mode while the 8xc51 is configured in its mode 0 serial interface mode. the drdy line from the ad7712 is connected to the port p1.2 input of the 8xc51 so the drdy line is polled by the 8xc51. the drdy line can be connected to the int1 input of the 8xc51 if an interrupt driven system is preferred. p1.0 p3.0 p3.1 p1.1 p1.2 p1.3 dv dd 8xc51 ad7712 sdata a0 rfs tfs mode drdy sync sclk figure 18. ad7712 to 8xc51 interface table vii shows some typical 8xc51 code used for a single 24-bit read from the output register of the ad7712. table viii shows some typical code for a single write operation to the con- trol register of the ad7712. the 8xc51 outputs the lsb first in a write operation while the ad7712 expects the msb first, so the data to be transmitted has to be rearranged before being written to the output serial register. similarly, the ad7712 out- puts the msb first during a read operation while the 8xc51 expects the lsb first. therefore, the data which is read into the serial buffer needs to be rearranged before the correct data word from the ad7712 is available in the accumulator. table vii. 8xc51 code for reading from the ad7712 mov scon,#00010001b; configure 8051 for mode 0 operation mov ie,#00010000b; disable all interrupts setb 90h; set p1.0, used as rfs setb 91h; set p1.1, used as tfs setb 93h; set p1.3, used as a0 mov r1,#003h; sets number of bytes to be read in a read operation mov r0,#030h; start address for where bytes will be loaded mov r6,#004h; use p1.2 as drdy wait: nop; mov a,p1; read port 1 anl a,r6; mask out all bits except drdy jz read; if zero read sjmp wait; otherwise keep polling read: clr 90h; bring rfs low clr 98h; clear receive flag poll: jb 98h, read1 tests receive interrupt flag sjmp poll read 1: mov a,sbuf; read buffer rlc a; rearrange data mov b.0,c; reverse order of bits rlc a; mov b.1,c; rlc a; mov b.2,c; rlc a; mov b.3,c; rlc a; mov b.4,c; rlc a; mov b.5,c; rlc a; mov b.6,c; rlc a; mov b.7,c; mov a,b; mov @r0,a; write data to memory inc r0; increment memory location dec r1 decrement byte counter mov a,r1 jz end jump if zero jmp wait fetch next byte end: setb 90h bring rfs high fin: sjmp fin
rev. e C26C ad7712 table viii. 8xc51 code for writing to the ad7712 mov scon,#00000000b; configure 8051 for mode 0 operation & enable serial reception mov ie,#10010000b; enable transmit interrupt mov ip,#00010000b; prioritize the transmit interrupt setb 91h; bring tfs high setb 90h; bring rfs high mov r1,#003h; sets number of bytes to be written in a write operation mov r0,#030h; start address in ram for bytes mov a,#00h; clear accumulator mov sbuf,a; initialize the serial port wait: jmp wait; wait for interrupt int routine: nop; interrupt subroutine mov a,r1; load r1 to accumulator jz fin; if zero jump to fin dec r1; decrement r1 byte counter mov a,@r; move byte into the accumulator inc r0; increment address rlc a; rearrange datafrom lsb first to msb first mov b.0,c; rlc a; mov b.1,c; rlc a; mov b.2,c; rlc a; mov b.3,c; rlc a; mov b.4,c; rlc a; mov b.5,c; rlc a; mov b.6,c; rlc a: mov b.7,c; mov a,b; clr 93h; bring a0 low clr 91h; bring tfs low mov sbuf,a; write to serial port reti; return from subroutine fin: setb 91h; set tfs high setb 93h; set a0 high reti; return from interrupt subroutine ad7712 to 68hc11 interface figure 19 shows an interface between the ad7712 and the 68hc11 microcontroller. the ad7712 is configured for its external clocking mode while the spi port is used on the 68hc11 which is in its single chip mode. the drdy line from the ad7712 is connected to the port pc0 input of the 68hc11 so the drdy line is polled by the 68hc11. the drdy line can be connected to the irq input of the 68hc11 if an inter- rupt driven system is preferred. the 68hc11 mosi and miso lines should be configured for wired-or operation. depending on the interface configuration, it may be necessary to provide bidirectional buffers between the 68hc11s mosi and miso lines. the 68hc11 is configured in the master mode with its cpol bit set to a logic zero and its cpha bit set to a logic one. with a 10 mhz master clock on the ad7712, the interface will operate with all four serial clock rates of the 68hc11. ad7712 sdata sclk a0 rfs tfs pc0 miso sck pc1 pc2 mode pc3 drdy sync 68hc11 mosi ss dv dd dv dd figure 19. ad7712 to 68hc11 interface ad7712 to adsp-2105 interface an interface circuit between the ad7712 and the adsp-2105 microprocessor is shown in figure 20. in this interface, the ad7712 is configured for its self-clocking mode while the rfs and tfs pins of the adsp-2105 are configured as inputs and the adsp-2105 serial clock line is also configured as an input. when the adsp-2105s serial clock is configured as an input it needs a couple of clock pulses to initialize itself correctly before accepting data. therefore, the first read from the ad7712 may not read correct data. in the interface shown, a read operation to the ad7712 accesses either the output register or the calibra- tion registers. data cannot be read from the control register. a write operation always writes to the control or calibration registers. drdy is used as the frame synchronization pulse for read op- erations from the output register and it is decoded with a0 to drive the rfs inputs of both the ad7712 and the adsp-2105. the latched a0 line drives the tfs inputs of both the ad7712 and the adsp-2105 as well as the ad7712 a0 input. ad7712 sdata sclk a0 rfs tfs dr sclk mode a0 drdy adsp-2105 dt dmwr tfs rfs dv dd d q q 74hc74 figure 20. ad7712 to adsp-2105 interface
2 C27C rev. e ad7712 clock generation serial interface output register charge-balancing a/d converter auto-zeroed s C d modulator digital filter ad7712 agnd dgnd mode sdata sclk a0 mclk out mclk in ain1(+) ain1(C) ref in (C) ref in (+) sync 4.5 m a a = 1 C 128 drdy tfs rfs ref out 2.5v reference voltage attenuation ain2 standby control register v ss 500 v pga m u x av dd av dd dv dd analog +5v supply v bias 4C20ma loop figure 21. 4C20 ma loop measurement using the ad7712 applications 4C20 ma loop the ad7712s high level input can be used to measure the current in 4C20 ma loop applications as shown in figure 21. in this case, the system calibration capabilities of the ad7712 can be used to remove the offset caused by the 4 ma flowing through the 500 w resistor. the ad7712 can handle an input span as low as 3.2 v ref (= 8 v with a v ref of +2.5 v) even though the nominal input voltage range for the input is 10 v. therefore, the full span of the a/d converter can be used for measuring the current between 4 ma and 20 ma.
rev. e C28C ad7712 c1656dC0C7/98 printed in u.s.a. outline dimensions dimensions shown in inches and (mm). plastic dip (n-24) 24 112 13 0.280 (7.11) 0.240 (6.10) pin 1 1.275 (32.30) 1.125 (28.60) 0.150 (3.81) min 0.200 (5.05) 0.125 (3.18) seating plane 0.022 (0.558) 0.014 (0.356) 0.060 (1.52) 0.015 (0.38) 0.210 (5.33) max 0.070 (1.77) 0.045 (1.15) 0.100 (2.54) bsc 0.325 (8.25) 0.300 (7.62) 0.015 (0.381) 0.008 (0.204) 0.195 (4.95) 0.115 (2.93) cerdip (q-24) 24 1 12 13 0.310 (7.87) 0.220 (5.59) pin 1 0.005 (0.13) min 0.098 (2.49) max seating plane 0.023 (0.58) 0.014 (0.36) 0.200 (5.08) max 1.280 (32.51) max 0.150 (3.81) min 0.200 (5.08) 0.125 (3.18) 0.100 (2.54) bsc 0.060 (1.52) 0.015 (0.38) 0.070 (1.78) 0.030 (0.76) 15 8 0 8 0.320 (8.13) 0.290 (7.37) 0.015 (0.38) 0.008 (0.20) soic (r-24) 24 13 12 1 0.6141 (15.60) 0.5985 (15.20) 0.4193 (10.65) 0.3937 (10.00) 0.2992 (7.60) 0.2914 (7.40) pin 1 seating plane 0.0118 (0.30) 0.0040 (0.10) 0.0192 (0.49) 0.0138 (0.35) 0.1043 (2.65) 0.0926 (2.35) 0.0500 (1.27) bsc
package/price information cmos, 24-bit sigma-delta, signal conditioning adc with 2 analog input channels. * this price is provided for budgetary purposes as recommended list price in u.s. dollars per unit in the stated volume. pricing displayed for evaluation boards and kits is based on 1-piece pricing. view pricing and availability for further information. model status package description pin count temperature range price* (100-499) AD7712ACHIPS production chips/die sales - commercial $17.05 ad7712an production plastic/epoxy dip 24 commercial $17.05 ad7712aq production cerdip glass seal 24 commercial $21.78 ad7712ar production std s.o. pkg (soic) 24 commercial $17.05 ad7712ar-reel production std s.o. pkg (soic) 24 commercial - ad7712ar-reel7 production std s.o. pkg (soic) 24 commercial - ad7712sq production cerdip glass seal 24 commercial $63.53 eval-ad7712eb production no conversion data from cos - commercial $165.00

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